The present invention relates to a semiconductor device. More particularly, it relates to a technology effectively applicable to a semiconductor device having a nonvolatile memory.
As electrically writable/erasable nonvolatile semiconductor storage devices, EEPROMs (Electrically Erasable and Programmable Read Only Memories) have been widely used. The storage devices (memories) typified by currently and widely used flash memories have conductive floating gate electrodes surrounded by an oxide film and trapping insulation films under gate electrodes of MISFETs. The storage devices use charge accumulation states at the floating gates and the trapping insulation film as stored information, and read out the information as a threshold value of each transistor. The trapping insulation film denotes an insulation film capable of accumulating electric charges. As one example thereof, mention may be made of a silicon nitride film.
Injection/discharge of charges into such charge accumulation regions causes each MISFET to be shifted in threshold value and to operate as a storage element. The flash memories include a split gate type cell using a MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor) film. Such a memory has the following advantages: use of a silicon nitride film as a charge accumulation region leads to an excellent data holding reliability because electric charges are accumulated discretely as compared with a conductive floating gate, and the excellent data holding reliability can reduce the film thickness of the oxide films over and under the silicon nitride film, which enables a lower voltage for write/erase operation; and other advantages.
Japanese Unexamined Patent Publication No. 2009-81316 (Patent Literature 1) describes the technology regarding a nonvolatile semiconductor storage device which has a first insulation film disposed over a channel between source/drain diffusion layers, a charge accumulation layer disposed over the first insulation film, a second insulation film including plurality of layers, and disposed over the charge accumulation layer, and a control gate electrode disposed over the second insulation film.
[Patent Literature 1] Japanese Unexamined Patent Publication No. 2009-81316